FRM PLL
Introduction
This PLL was first published in March 1983 in Free Radio Magazine and was
re-published a year later in the same magazine. It uses the well known 4046 as
PLL and a CD4059 as programmable divider. The RF signal from an oscillator is
fed to a 74S112 (a divide-by-4 section). Next it is followed by a divide-by-16
and the programmable divider. When a frequency of 100[MHz] is selected e.g. by
using BCD rotary switches, this leads to the following:
100[MHz]/4/16=1.5625[kHz]. This signal's phase is compared to a crystal
oscillator, build around a CD4060 and a 6.4[MHz] crystal (which also has a
frequency of 1.5625[kHz] at its /4096 output). When both signals are out of
phase the 4046 will give of a voltage that can be used to control a VFO. The
most tricky part is this voltagesignal. This signal should have a large
amplitude to adjust the VFO to all frequencies (90-109.9[MHz]), but this signal
also needs to be filtered out, because otherwise it will be audible for any
listener. Further more the signal needs to be delayed, because otherwise the
audio-modulation is also adjusted, making it in-audible! The filter in this
schematic is built around four opamps (LM324), giving it a range of 0 to 8[V] to
control the varicapdiode in the VFO. If the frequency is to be adjusted by BCD
rotary switches, make sure to set the voltage at the point marked TP in the
layout to +/-4[V], do this by adjusting the variable capacitor in the VFO. After
doing this, you should be able to set the frequency in a range of around 10[MHz]
(5[MHz] up and 5[MHz] down). When a larger frequency range is needed, place some
varicapdiodes parallel to eachother in the VFO. The 4046 also has another opamp
(a CA3140) connected to it, this opamp will make sure the PLL searches its
complete range to match the VFO to the reference signal. This will happen so
fast (in half a second) that no extra components are required to turn the
transmitter off, when not locked to the desired frequency. By trimming the
10[kOhm] variable resistor any interference in the audioband can be eliminated.
Making it work
When connecting the point marked A with point B will give a frequency range of
100.00-109.90[MHz] and connecting the points A and C will give a frequency range
of 90.00-99.90[MHz]. You can use a simple switch to cover the entire range of
90.0-109.90[MHz] (see illustration 1). Two BCD rotary switches can be used to
set the 1[MHz] settings and the 100[kHz] settings for this PLL (see also
illustration 1). Off course one can also use a simple switch, which has 10
connections, see illustration 2. The diodes in illustration 2 are ordinary
diodes like the 1N4148 or equal. At pen 1 of the CD4046 a lockindication led can
be connected, see illustration 3 (note that this circuitry is not present on the
PLL schematic!).
